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[ DevCourseWeb com ] Udemy - UVM for Verification Part 3 - Register Abstraction Layer (RAL)
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1. Adding Register and Memory to Verification Environment
1. Course Overview.mp4
1. Course Overview.srt
10. Components of Register model P2.mp4
10. Components of Register model P2.srt
11. Components of Register model P3.mp4
11. Components of Register model P3.srt
12. Notes.html
13. Typical Learning Path.mp4
13. Typical Learning Path.srt
14. Understanding different types of registers.mp4
14. Understanding different types of registers.srt
15. Implementation of Register in Verification Environmnet P1.mp4
15. Implementation of Register in Verification Environmnet P1.srt
16. Implementation of Register in Verification Environmnet P2.mp4
16. Implementation of Register in Verification Environmnet P2.srt
17. Alternate way of adding configure function.mp4
17. Alternate way of adding configure function.srt
18. Summary Configure function.mp4
18. Summary Configure function.srt
19. Implementation of Register in Verification Environmnet P3.mp4
19. Implementation of Register in Verification Environmnet P3.srt
2. Agenda.mp4
2. Agenda.srt
20. Code.html
21. Slides.html
22. Adding Register with two fields.mp4
22. Adding Register with two fields.srt
23. Code.html
24. Adding Register with reserved bits.mp4
24. Adding Register with reserved bits.srt
25. Code.html
26. Different Access Policy P1.mp4
26. Different Access Policy P1.srt
27. Different Access Policy P2.mp4
27. Different Access Policy P2.srt
28. Different Access Policy P3.mp4
28. Different Access Policy P3.srt
29. Different Access Policy P4.mp4
29. Different Access Policy P4.srt
3. Advantage of UVM RAL P1.mp4
3. Advantage of UVM RAL P1.srt
30. Notes.html
31. Adding Memory P1.mp4
31. Adding Memory P1.srt
32. Adding Memory P2.mp4
32. Adding Memory P2.srt
33. Code.html
34. Slides.html
35. A11.html
36. A12.html
4. Advantage of UVM RAL P2.mp4
4. Advantage of UVM RAL P2.srt
5. Advantage of UVM RAL P3.mp4
5. Advantage of UVM RAL P3.srt
6. Advantage of UVM RAL P4.mp4
6. Advantage of UVM RAL P4.srt
7. When to use RAL in Verification environment.mp4
7. When to use RAL in Verification environment.srt
8. Code.html
9. Components of Register model P1.mp4
9. Components of Register model P1.srt
2. Adding Register Block
1. Agenda.mp4
1. Agenda.srt
2. Adding Register Block P1.mp4
2. Adding Register Block P1.srt
3. Adding Register Block P2.mp4
3. Adding Register Block P2.srt
4. Adding Register Block P3.mp4
4. Adding Register Block P3.srt
5. Code.html
6. Slides.html
7. A21.html
3. Understanding Adapter
1. Agenda.mp4
1. Agenda.srt
10. Adapter code with Protocol Specific ports P1.mp4
10. Adapter code with Protocol Specific ports P1.srt
11. Adapter code with Protocol Specific ports P2.mp4
11. Adapter code with Protocol Specific ports P2.srt
12. Summary.mp4
12. Summary.srt
13. Slides.html
14. A31.html
2. Usage of adapter.mp4
2. Usage of adapter.srt
3. Typical flow.mp4
3. Typical flow.srt
4. Structure of uvm_reg_bus_op struct.mp4
4. Structure of uvm_reg_bus_op struct.srt
5. Complete flow.mp4
5. Complete flow.srt
6. Understanding reg2bus.mp4
6. Understanding reg2bus.srt
7. Understanding bus2reg.mp4
7. Understanding bus2reg.srt
8. Adapter code with native memory ports P1.mp4
8. Adapter code with native memory ports P1.srt
9. Adapter code with native memory ports P2.mp4
9. Adapter code with native memory ports P2.srt
4. Different Register Method
1. Agenda.mp4
1. Agenda.srt
10. Adding Agent.mp4
10. Adding Agent.srt
11. Adding Register Model.mp4
11. Adding Register Model.srt
12. Adding env + uvm test top + testbench top.mp4
12. Adding env + uvm test top + testbench top.srt
13. Executing Code.mp4
13. Executing Code.srt
14. Design Code.html
15. Understanding Desired and Mirrored Values.mp4
15. Understanding Desired and Mirrored Values.srt
16. Different register methods.mp4
16. Different register methods.srt
17. Working with Desired Value.mp4
17. Working with Desired Value.srt
18. Testbench Code.html
19. Working with Mirrored Value.mp4
19. Working with Mirrored Value.srt
2. Types of Predictor Implicit Predictor.mp4
2. Types of Predictor Implicit Predictor.srt
20. Testbench Code.html
21. Understanding predict and mirror.mp4
21. Understanding predict and mirror.srt
22. Demonstration.mp4
22. Demonstration.srt
23. Testbench Code.html
24. Single Read and Write Transaction.mp4
24. Single Read and Write Transaction.srt
25. Multiple Read and Write Transaction.mp4
25. Multiple Read and Write Transaction.srt
26. Testbench Code.html
27. Using randomize.mp4
27. Using randomize.srt
28. Testbench Code.html
29. Understanding Reset Methods.mp4
29. Understanding Reset Methods.srt
3. Types of Predictor Explicit Predictor.mp4
3. Types of Predictor Explicit Predictor.srt
30. Demonstration.mp4
30. Demonstration.srt
31. Testbench Code.html
32. Connecting reset methods to DUT.mp4
32. Connecting reset methods to DUT.srt
33. Testbench Code.html
34. A41.html
4. Types of Predictor Passive Predictor.mp4
4. Types of Predictor Passive Predictor.srt
5. Slide.html
6. Driver Sequencer Communication.mp4
6. Driver Sequencer Communication.srt
7. Code.html
8. Understanding Design.mp4
8. Understanding Design.srt
9. Adding Driver + Sequencer.mp4
9. Adding Driver + Sequencer.srt
5. Different ways of accessing Register and Memories
1. Agenda.mp4
1. Agenda.srt
10. Peek and Poke P1.mp4
10. Peek and Poke P1.srt
11. Peek and Poke P2.mp4
11. Peek and Poke P2.srt
12. Design Code.html
13. Testbench Code.html
14. A51.html
2. Type of access methods p1 Frontdoor.mp4
2. Type of access methods p1 Frontdoor.srt
3. Type of access methods p2 Backdoor.mp4
3. Type of access methods p2 Backdoor.srt
4. Frontdoor Demonstration.mp4
4. Frontdoor Demonstration.srt
5. Testbench Code.html
6. Fundamentals of Backdoor access.mp4
6. Fundamentals of Backdoor access.srt
7. Demonstration.mp4
7. Demonstration.srt
8. Design Code.html
9. Testbench Code.html
6. Explicit Predictor and Coverage
1. Agenda.mp4
1. Agenda.srt
10. Coverage analysis P1.mp4
10. Coverage analysis P1.srt
11. Coverage analysis P2.mp4
11. Coverage analysis P2.srt
12. Coverage analysis P3.mp4
12. Coverage analysis P3.srt
13. Design Code.html
14. Testbench Code.html
15. run.do.html
2. Understanding Design for Explicit Predictor.mp4
2. Understanding Design for Explicit Predictor.srt
3. Building Verification env P1.mp4
3. Building Verification env P1.srt
4. Building Verification env P2.mp4
4. Building Verification env P2.srt
5. Building Verification env P3.mp4
5. Building Verification env P3.srt
6. Building Verification env P4.mp4
6. Building Verification env P4.srt
7. Testing Code.mp4
7. Testing Code.srt
8. Design Code.html
9. Testbench Code.html
7. Working with Memories
1. Agenda.mp4
1. Agenda.srt
10. Design Code.html
11. Testbench Code.html
12. Coverage computation for memory P1.mp4
12. Coverage computation for memory P1.srt
13. Coverage computation for memory P2.mp4
13. Coverage computation for memory P2.srt
14. Design Code.html
15. Testbench Code.html
2. Understanding Design.mp4
2. Understanding Design.srt
3. Building DRV + MON + SCO + AGENT.mp4
3. Building DRV + MON + SCO + AGENT.srt
4. Building Register model.mp4
4. Building Register model.srt
5. Adding Register sequence Single Transaction.mp4
5. Adding Register sequence Single Transaction.srt
6. Adding Register sequence Multiple Transactions.mp4
6. Adding Register sequence Multiple Transactions.srt
7. Design Code.html
8. Testbench Code.html
9. Burst Transactions.mp4
9. Burst Transactions.srt
8. Complete Project
1. Agenda.mp4
1. Agenda.srt
10. Design Code.html
11. Testbench Code.html
12. A81.html
13. A82.html
2. Understanding Design P1.mp4
2. Understanding Design P1.srt
3. Understand Design P2.mp4
3. Understand Design P2.srt
4. Building Verification environment P1.mp4
4. Building Verification environment P1.srt
5. Building Verification environment P2.mp4
5. Building Verification environment P2.srt
6. Building Register model P1.mp4
6. Building Register model P1.srt
7. Building Register model P2.mp4
7. Building Register model P2.srt
8. Adding testbench top.mp4
8. Adding testbench top.srt
9. Testing DUT.mp4
9. Testing DUT.srt
Bonus Resources.txt
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