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[ DevCourseWeb com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

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Name:[ DevCourseWeb com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

Infohash: 9CB8F080C5594D1A696EB2FE4646269C509ED2DE

Total Size: 2.96 GB

Seeds: 0

Leechers: 0

Stream: Watch Full Movies @ LimeMovies

Last Updated: 2025-10-11 16:10:09 (Update Now)

Torrent added: 2022-05-02 22:05:11






Torrent Files List


Get Bonus Downloads Here.url (Size: 2.96 GB) (Files: 131)

 Get Bonus Downloads Here.url

0.18 KB

 ~Get Your Files Here !

  1 - Section 0 Course Framework

   1 - Interface Type English.vtt

1.99 KB

   1 - Interface Type.mp4

11.34 MB

   2 - Course Framework English.vtt

8.36 KB

   2 - Course Framework.mp4

47.72 MB

  10 - AXI Stream Master Interface with Vivado Template

   54 - Agenda English.vtt

0.76 KB

   54 - Agenda.mp4

2.32 MB

   55 - Creating AXIS Master Interface P1 English.vtt

22.38 KB

   55 - Creating AXIS Master Interface P1.mp4

145.25 MB

   56 - Creating AXIS Master Interface P2 English.vtt

4.97 KB

   56 - Creating AXIS Master Interface P2.mp4

35.32 MB

   57 - Code.html

1.32 KB

  11 - AXIS Slave Interface with Verilog

   58 - Agenda English.vtt

0.60 KB

   58 - Agenda.mp4

1.98 MB

   59 - Building AXIS Slave Interface with Verilog P1 English.vtt

10.98 KB

   59 - Building AXIS Slave Interface with Verilog P1.mp4

37.08 MB

   60 - Building AXIS Slave Interface with Verilog P2 English.vtt

13.19 KB

   60 - Building AXIS Slave Interface with Verilog P2.mp4

61.62 MB

   61 - Building AXIS Slave Interface with Verilog P3 English.vtt

4.62 KB

   61 - Building AXIS Slave Interface with Verilog P3.mp4

23.33 MB

   62 - Code and BD.html

2.11 KB

  12 - AXIS Master Slave Interface with Verilog

   63 - Agenda English.vtt

0.90 KB

   63 - Agenda.mp4

2.37 MB

   64 - Building AXIS Master Slave Interface with Verilog P1 English.vtt

17.24 KB

   64 - Building AXIS Master Slave Interface with Verilog P1.mp4

57.49 MB

   65 - Building AXIS Master Slave Interface with Verilog P2 English.vtt

7.20 KB

   65 - Building AXIS Master Slave Interface with Verilog P2.mp4

45.10 MB

   66 - Code and BD.html

2.09 KB

   67 - Code and BD.html

2.52 KB

  13 - Understanding Common Errors

   68 - Common Error 1 English.vtt

2.76 KB

   68 - Common Error 1.mp4

19.06 MB

   69 - Common Error 2 English.vtt

4.09 KB

   69 - Common Error 2.mp4

24.78 MB

  2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports

   3 - Agenda English.vtt

0.57 KB

   3 - Agenda.mp4

2.26 MB

   4 - Slave Lite Interface without I O Ports P1 Creating IP English.vtt

10.07 KB

   4 - Slave Lite Interface without I O Ports P1 Creating IP.mp4

55.29 MB

   5 - Slave Lite Interface without I O Ports P2 Creating IP English.vtt

7.94 KB

   5 - Slave Lite Interface without I O Ports P2 Creating IP.mp4

49.33 MB

   6 - Slave Lite Interface without I O Ports P3 Creating IP English.vtt

5.84 KB

   6 - Slave Lite Interface without I O Ports P3 Creating IP.mp4

39.17 MB

   7 - Slave Lite Interface without I O Ports P4 Creating C Application English.vtt

11.26 KB

   7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4

76.31 MB

   8 - Slave Lite Interface without I O Ports P5 Creating C Application English.vtt

4.78 KB

   8 - Slave Lite Interface without I O Ports P5 Creating C Application.mp4

38.35 MB

   9 - C Code.html

0.77 KB

  3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports

   10 - Agenda English.vtt

0.73 KB

   10 - Agenda.mp4

2.64 MB

   11 - Adding Output port to Slave Lite Interface P1 English.vtt

8.08 KB

   11 - Adding Output port to Slave Lite Interface P1.mp4

50.31 MB

   12 - Adding Output port to Slave Lite Interface P2 English.vtt

4.99 KB

   12 - Adding Output port to Slave Lite Interface P2.mp4

37.13 MB

   13 - Adding Output port to Slave Lite Interface P3 English.vtt

4.19 KB

   13 - Adding Output port to Slave Lite Interface P3.mp4

33.58 MB

   14 - Adding Input and Output ports to Slave Lite Interface P1 English.vtt

7.54 KB

   14 - Adding Input and Output ports to Slave Lite Interface P1.mp4

44.79 MB

   15 - Adding Input and Output ports to Slave Lite Interface P2 English.vtt

5.58 KB

   15 - Adding Input and Output ports to Slave Lite Interface P2.mp4

49.34 MB

   16 - Adding Input and Output ports to Slave Lite Interface P3 English.vtt

2.74 KB

   16 - Adding Input and Output ports to Slave Lite Interface P3.mp4

22.98 MB

  4 - Understanding AXI4-Lite Signals

   17 - Agenda English.vtt

0.94 KB

   17 - Agenda.mp4

2.26 MB

   18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1 English.vtt

8.53 KB

   18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1.mp4

24.55 MB

   19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2 English.vtt

6.63 KB

   19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2.mp4

23.98 MB

   20 - Understanding Mandatory Signal Master read from Slave (Reading Ops) English.vtt

3.87 KB

   20 - Understanding Mandatory Signal Master read from Slave (Reading Ops).mp4

12.00 MB

   21 - Other Signals in Slave Lite Interface English.vtt

12.03 KB

   21 - Other Signals in Slave Lite Interface.mp4

89.56 MB

   22 - Block Design used in Demonstration English.vtt

5.13 KB

   22 - Block Design used in Demonstration.mp4

37.97 MB

   23 - Analyzing Signals on ILA Probe English.vtt

15.41 KB

   23 - Analyzing Signals on ILA Probe.mp4

98.17 MB

  5 - Adding AXI Lite Interface for existing Verilog Code

   24 - Agenda English.vtt

1.46 KB

   24 - Agenda.mp4

4.98 MB

   25 - Add Existing RTL Delay Generator P1 English.vtt

15.67 KB

   25 - Add Existing RTL Delay Generator P1.mp4

93.72 MB

   26 - Add Existing RTL Delay Generator P2 English.vtt

5.92 KB

   26 - Add Existing RTL Delay Generator P2.mp4

43.79 MB

   27 - Adding Existing RTL Multiplier P1 English.vtt

12.57 KB

   27 - Adding Existing RTL Multiplier P1.mp4

83.11 MB

   28 - Adding Existing RTL Multiplier P2 English.vtt

4.65 KB

   28 - Adding Existing RTL Multiplier P2.mp4

43.26 MB

   29 - Adding Exisitng RTL COMPLEX FSM P1 English.vtt

10.00 KB

   29 - Adding Exisitng RTL COMPLEX FSM P1.mp4

54.73 MB

  6 - Adding Interrupts to Slave Lite Interfaces

   30 - Agenda English.vtt

0.88 KB

   30 - Agenda.mp4

1.90 MB

   31 - Fundamentals of Interrupt C Application English.vtt

14.48 KB

   31 - Fundamentals of Interrupt C Application.mp4

80.58 MB

   32 - Adding Interrupt with RTL P1 English.vtt

13.69 KB

   32 - Adding Interrupt with RTL P1.mp4

90.41 MB

   33 - Adding Interrupt with RTL P2 English.vtt

17.62 KB

   33 - Adding Interrupt with RTL P2.mp4

149.24 MB

   34 - Code.html

2.11 KB

  7 - Adding Interrupts with Vivado Template

   35 - Agenda English.vtt

0.92 KB

   35 - Agenda.mp4

2.11 MB

   36 - Using Vivado Interrupt Template Code P1 English.vtt

17.86 KB

   36 - Using Vivado Interrupt Template Code P1.mp4

100.08 MB

   37 - Using Vivado Interrupt Template Code P2 English.vtt

29.05 KB

   37 - Using Vivado Interrupt Template Code P2.mp4

213.64 MB

   38 - Code.html

1.81 KB

   39 - Modifying Delay of the Vivado Interrupt Template English.vtt

8.29 KB

   39 - Modifying Delay of the Vivado Interrupt Template.mp4

55.32 MB

   40 - Generating Continuous Interrupt P1 English.vtt

6.10 KB

   40 - Generating Continuous Interrupt P1.mp4

41.46 MB

   41 - Generating Continuous Interrupt P2 English.vtt

2.68 KB

   41 - Generating Continuous Interrupt P2.mp4

21.83 MB

   42 - Blinking Effect with Interrupt English.vtt

18.71 KB

   42 - Blinking Effect with Interrupt.mp4

150.74 MB

   43 - Code.html

2.35 KB

  8 - Adding Master Interface

   44 - Agenda English.vtt

0.77 KB

   44 - Agenda.mp4

2.09 MB

   45 - Creating Master Interface with Vivado Template P1 English.vtt

21.28 KB

   45 - Creating Master Interface with Vivado Template P1.mp4

162.54 MB

   46 - Creating Master Interface with Vivado Template P2 English.vtt

7.57 KB

   46 - Creating Master Interface with Vivado Template P2.mp4

62.70 MB

   47 - Code.html

0.56 KB

  9 - AXI Stream Slave Interface with Vivado Template

   48 - Agenda English.vtt

0.95 KB

   48 - Agenda.mp4

2.65 MB

   49 - Building AXIS Slave Interface P1 English.vtt

24.04 KB

   49 - Building AXIS Slave Interface P1.mp4

138.81 MB

   50 - Building AXIS Slave Interface P2 English.vtt

7.64 KB

   50 - Building AXIS Slave Interface P2.mp4

65.48 MB

   51 - Code.html

0.76 KB

   52 - Building Complex FSM with existing FSM for AXIS English.vtt

9.68 KB

   52 - Building Complex FSM with existing FSM for AXIS.mp4

63.95 MB

   53 - Code.html

3.33 KB

  Bonus Resources.txt

0.38 KB

  Building Custom AXI Interface Peripherals for ZYNQ Devices.jpg

10.76 KB

  Building Custom AXI Interface Peripherals for ZYNQ Devices.txt

6.45 KB
 

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