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  01 - Introduction

   001 Preview_en.vtt

   002 Introduction to Serial Communication_en.vtt

   003 Limitations of parallel communication and Advantage of Serial communication_en.vtt

   004 Synchronous & Asynchronous Serial communication_en.vtt

  02 - Introduction to UART

   001 What is UART_en.vtt

   002 Data format of UART_en.vtt

   003 Transmission & Reception operations in UART_en.vtt

   004 Block diagram for UART_en.vtt

  03 - Implementation of UART modules

   001 Baud rate generator_en.vtt

   002 Verilog HDL for Baud rate generator_en.vtt

   003 FSM for UART Transmitter_en.vtt

   004 FSM for UART Receiver_en.vtt

   005 Test bench environment_en.vtt

   006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt

   007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt

   008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt

  Bonus Resources.txt