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[ DevCourseWeb com ] Udemy - VLSI - Essential concepts and detailed interview guide
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01 - Physical Design Flow Overview
001 Floor-Planning Steps.mp4
001 Floor-Planning Steps_en.vtt
002 Netlist Binding And Placement Optimization.mp4
002 Netlist Binding And Placement Optimization_en.vtt
003 Clock Net Shielding.mp4
003 Clock Net Shielding_en.vtt
004 Route - DRC Clean - Parasitics Extraction - Final STA.mp4
004 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt
02 - Floorplanning
001 Utilization Factor And Aspect Ratio.mp4
001 Utilization Factor And Aspect Ratio_en.vtt
002 Concept of Pre-placed Cells.mp4
002 Concept of Pre-placed Cells_en.vtt
003 Power Planning.mp4
003 Power Planning_en.vtt
004 Pin Placement And Logical Cell Placement Blockage.mp4
004 Pin Placement And Logical Cell Placement Blockage_en.vtt
03 - Placement
001 Netlist Binding And Placement.mp4
001 Netlist Binding And Placement_en.vtt
002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4
002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt
003 Optimize Placement Continued.mp4
003 Optimize Placement Continued_en.vtt
04 - Timing Analysis With Ideal Clocks
001 Setup Time Analysis And Introduction To Flip-Flop Setup Time.mp4
001 Setup Time Analysis And Introduction To Flip-Flop Setup Time_en.vtt
002 Setup Timing Analysis With Multiple Clocks.mp4
002 Setup Timing Analysis With Multiple Clocks_en.vtt
003 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4
003 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt
004 Data Slew Check.mp4
004 Data Slew Check_en.vtt
05 - Clock Tree Synthesis - Introduction And Quality Check Parameters
001 Introduction To Clock Tree Synthesis.mp4
001 Introduction To Clock Tree Synthesis_en.vtt
002 Duty Cycle And Latency Check.mp4
002 Duty Cycle And Latency Check_en.vtt
003 Latency And Power Check.mp4
003 Latency And Power Check_en.vtt
004 Power And Crosstalk Quality Check.mp4
004 Power And Crosstalk Quality Check_en.vtt
005 Glitch Quality Check.mp4
005 Glitch Quality Check_en.vtt
06 - H-Tree
001 H-Tree Algorithm And Skew Check.mp4
001 H-Tree Algorithm And Skew Check_en.vtt
002 H-Tree Pulse Width And Duty Cycle Check.mp4
002 H-Tree Pulse Width And Duty Cycle Check_en.vtt
003 H-Tree Latency And Power Check.mp4
003 H-Tree Latency And Power Check_en.vtt
07 - Clock Tree Modelling and Observations
001 Clock Tree Modelling.mp4
001 Clock Tree Modelling_en.vtt
002 Clock Tree Building.mp4
002 Clock Tree Building_en.vtt
003 Clock Tree Observations.mp4
003 Clock Tree Observations_en.vtt
08 - Buffered H-Tree
001 H-Tree Buffering Observations.mp4
001 H-Tree Buffering Observations_en.vtt
002 H-Tree Pulse Width Check And Issues With Regular Buffers.mp4
002 H-Tree Pulse Width Check And Issues With Regular Buffers_en.vtt
003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution.mp4
003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution_en.vtt
004 H-Tree Clock Buffers And Pulse Width Check.mp4
004 H-Tree Clock Buffers And Pulse Width Check_en.vtt
005 Dynamic Power And Short Circuit Power.mp4
005 Dynamic Power And Short Circuit Power_en.vtt
09 - Clock Tree Optimization Checklist
001 Optimization Checklist.mp4
001 Optimization Checklist_en.vtt
002 Leakage Current Reduction Technique.mp4
002 Leakage Current Reduction Technique_en.vtt
003 Optimized Clock Tree Power And Latency Check.mp4
003 Optimized Clock Tree Power And Latency Check_en.vtt
10 - Static Timing Analysis With Real Clocks
001 Static Timing Analysis With Real Clocks.mp4
001 Static Timing Analysis With Real Clocks_en.vtt
002 Impact Of Unbalanced Skew On Setup Time.mp4
002 Impact Of Unbalanced Skew On Setup Time_en.vtt
003 Impact Of Unbalanced Skew On Hold Time.mp4
003 Impact Of Unbalanced Skew On Hold Time_en.vtt
11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP
001 Introduction.mp4
001 Introduction_en.vtt
002 Dominant Lateral Capacitance.mp4
002 Dominant Lateral Capacitance_en.vtt
003 Noise Margin Voltage Parameters.mp4
003 Noise Margin Voltage Parameters_en.vtt
004 Lower Supply Voltage.mp4
004 Lower Supply Voltage_en.vtt
12 - Glitch Examples And Factors Affecting Glitch Height
001 Basic Crosstalk Glitch Example.mp4
001 Basic Crosstalk Glitch Example_en.vtt
002 Glitch Discharge With High Drive Strength PMOS Transistor.mp4
002 Glitch Discharge With High Drive Strength PMOS Transistor_en.vtt
003 Factors Affecting Glitch Height - Aggressor Drive Strength.mp4
003 Factors Affecting Glitch Height - Aggressor Drive Strength_en.vtt
004 Factors Affecting Glitch Height - Conclusion.mp4
004 Factors Affecting Glitch Height - Conclusion_en.vtt
13 - Tolerable Glitch Heights and Introduction to AC Noise Margin
001 Impacts Of Glitch.mp4
001 Impacts Of Glitch_en.vtt
002 Tolerable Glitch Heights Using DC Noise Margin.mp4
002 Tolerable Glitch Heights Using DC Noise Margin_en.vtt
003 AC Noise Margin.mp4
003 AC Noise Margin_en.vtt
004 Justification Of Load Impact And Conclusion.mp4
004 Justification Of Load Impact And Conclusion_en.vtt
14 - Crosstalk Delta Delay Analysis
001 Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction.mp4
001 Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction_en.vtt
002 Setup Timing Analysis Using Real Clocks.mp4
002 Setup Timing Analysis Using Real Clocks_en.vtt
003 Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction.mp4
003 Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction_en.vtt
004 Impact Of Crosstalk Delta Delay On Hold Timing.mp4
004 Impact Of Crosstalk Delta Delay On Hold Timing_en.vtt
15 - Noise Protection Technique
001 Shielding.mp4
001 Shielding_en.vtt
002 Spacing.mp4
002 Spacing_en.vtt
003 Drive Strength.mp4
003 Drive Strength_en.vtt
16 - Routing And Design Rule Check (DRC)
001 Introduction To Maze Routing - Lee's Algorithm.mp4
001 Introduction To Maze Routing - Lee's Algorithm_en.vtt
002 Design Rule Check.mp4
002 Design Rule Check_en.vtt
17 - Parasitics Extraction
001 Introduction To IEEE 1481-1999 SPEF Format.mp4
001 Introduction To IEEE 1481-1999 SPEF Format_en.vtt
002 SPEF Header Description, Physical Design Flow Conclusion And What Next !!.mp4
002 SPEF Header Description, Physical Design Flow Conclusion And What Next !!_en.vtt
18 - GENERATED CLOCKS DEFINITION AND CREATION
001 DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT.mp4
001 DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT_en.vtt
002 GENERATED CLOCKS USING MASTER CLOCK EDGES.mp4
002 GENERATED CLOCKS USING MASTER CLOCK EDGES_en.vtt
003 GENERATED CLOCK WAVEFORM DERIVATION.mp4
003 GENERATED CLOCK WAVEFORM DERIVATION_en.vtt
004 GENERATED CLOCK WITH SHIFTED EDGE.mp4
004 GENERATED CLOCK WITH SHIFTED EDGE_en.vtt
19 - BASICS OF MOS TRANSISTOR
001 INTRODUCTION TO VLSI ACADEMY.mp4
001 INTRODUCTION TO VLSI ACADEMY_en.vtt
002 GATE VOLTAGE AND ACCUMULATION OF NEGATIVE CHARGE.mp4
002 GATE VOLTAGE AND ACCUMULATION OF NEGATIVE CHARGE_en.vtt
003 N-CHANNEL FORMATION BETWEEN SOURCE AND DRAIN.mp4
003 N-CHANNEL FORMATION BETWEEN SOURCE AND DRAIN_en.vtt
004 IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT).mp4
004 IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT)_en.vtt
20 - SETUP & HOLD TIMING ANALYSIS
001 INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME.mp4
001 INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME_en.vtt
002 SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS.mp4
002 SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS_en.vtt
003 INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS.mp4
003 INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS_en.vtt
004 HOLD TIMING ANALYSIS CONCLUDED.mp4
004 HOLD TIMING ANALYSIS CONCLUDED_en.vtt
Bonus Resources.txt
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