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  01 - Physical Design Flow Overview

   001 Floor-Planning Steps_en.vtt

   002 Netlist Binding And Placement Optimization_en.vtt

   003 Placement Timing And Clock Tree Synthesis_en.vtt

   004 Clock Net Shielding_en.vtt

   005 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt

  02 - Floorplanning

   001 Utilization Factor And Aspect Ratio_en.vtt

   002 Concept Of Pre-Placed Cells_en.vtt

   003 De-coupling Capacitors_en.vtt

   004 Power Planning_en.vtt

   005 Pin Placement And Logical Cell Placement Blockage_en.vtt

  03 - Placement

   001 Net-list Binding And Placement_en.vtt

   002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt

   003 Optimize Placement Conitnued_en.vtt

  04 - Timing Analysis With Ideal Clocks

   001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time_en.vtt

   002 Introduction To Clock Jitter and Uncertainty_en.vtt

   003 Setup Timing Analysis with Multiple Clocks_en.vtt

   004 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt

   005 Data Slew Check_en.vtt

  05 - Clock Tree Synthesis And Signal Integrity

   001 Clock Tree Routing And Buffering using H-Tree Algorithm_en.vtt

   002 Crosstalk And Clock Net Shielding_en.vtt

   003 Static Timing Analysis With Real Clocks_en.vtt

   004 Hold Timing Analysis Concluded_en.vtt

   005 Multiple Clocks Setup Timing Analysis With Real Clocks_en.vtt

  06 - Routing And Design Rule Check (DRC)

   001 Introduction to Maze Routing - Lee's Algorithm_en.vtt

   002 Lee's Algorithm Conclusion_en.vtt

   003 Design Rule Check_en.vtt

  07 - Parasitics Extraction

   001 Introduction to IEEE 1481 - 1999 SPEF format_en.vtt

   002 SPEF Representation of a NET_en.vtt

   003 Distributed Resistance And Capacitance Representation in SPEF_en.vtt

   004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!_en.vtt

  Bonus Resources.txt