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RavindraBabu Ravula - GATE - 2021 - Digital Logic Design - CoursesGhar
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Name:RavindraBabu Ravula - GATE - 2021 - Digital Logic Design - CoursesGhar
Infohash: 9F2936C3C1E1154DABCDB5CF57A7266187F070F5
Total Size: 13.53 GB
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Last Updated: 2024-10-27 08:54:41 (Update Now)
Torrent added: 2021-06-22 09:30:33
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1.Instruction Note
1.Read Me First.pdf
2.Logic Functions
1.Basic properties of switching algebra.mkv
10.counting the number of functions and neutral functions.mkv
11.Venn diagram representation.mkv
12.Contact representation.mkv
13.Nested function.mkv
14.NAND gate and properties.mkv
15.NOR gate and properties.mkv
16.EX OR gate and properties.mkv
17.EX NOR gate and properties.mkv
18.Properties of EX-OR and EX-NOR.m4v
19.Minimum number of gates required for EX-OR and EX-NOR.m4v
2.Switching expressions and simplifications.mkv
20.Functionally completeness.mkv
21.Example 1 on functional completeness.mkv
22.Example 2 on functional completeness.mkv
23.Example 3 on functional completeness.mkv
24.Example 4 on functional completeness.mkv
25.Example 5 on functional completeness.mkv
26.Example 6 on functional completeness.mkv
27.Self dual functions.mkv
28.Number of self dual functions.mkv
29.Self dual functions are closed under complementation.mkv
3.Demorgans law and simplification..mkv
30.introduction to electronic gates.mkv
31.Positive and negative logic systems.mkv
32.Gate 2016 question on boolean algebra.mp4
33.Gate 2016 question on gray code function.mp4
4.Switching Functions..mkv
5.Canonical Sum of Products.mkv
6.Canonical Product of sums.mkv
7.Examples of canonical forms.mkv
8.Functional properties.mkv
9.Number of functions.mkv
3.Minimization
1.Introduction to minimization of Boolean expressions.mkv
10.Minimal SOP Example.m4v
11.Minimal POS.mp4
12.Examples on Minimal POS.mp4
13.Introduction to Dont cares.mp4
14.Examples on dont care set 1.mp4
15.Examples on dont care set 2.1.mp4
16.Examples on dont care set 2.2.mp4
17.Examples on dont care set 2.3.mp4
18.Examples on dont care set 2.4.mp4
19.Examples on dont care set 2.5.mp4
2.Irredundant or irreducible expressions.mkv
20.Examples on dont care set 3.mp4
21.Finding Minimal Expressions.mp4
22.Branching Technique for Minimising Cyclic Functions.mp4
23.Implicant and Prime Implicant Difference.mp4
24.Converting a Function into Self Dual.mp4
25.Combining Functions having Dont Cares.mp4
26.Prime Implicants and Dont Cares.mp4
27.Number of Minimal Expressions.mp4
28.Beautiful Question on Prime Implicant Chart.mp4
29.Variable Entrant Maps(VEM).mp4
3.K map introduction.mkv
30.Minimisation using VEM.mp4
31.Example on VEM.mp4
32.finding the free variables.mp4
33.Relationship between Minimal POS SOP in case of dont cares - 1.mp4
34.Relationship between Minimal POS SOP in case of dont cares - 2.mp4
35.Comparing independent variables in minimal SOP and POS.mp4 Lecture Title.mp4
36.Number of irredundant and minimal expressions.mp4
37.dont cares are never included in the prime Implicant chart.mp4
38.Functions nvolving Functions Example 1.mp4
39.Functions involving Functions example 2.m4v
4.K map simplification.mkv
40.Functions involving Functions Example 3.m4v
42.Examples on KMap.mkv
6.covering functions.mkv
7.Implicants and Prime Implicants.m4v
8.Essential Prime Implicants.m4v
9.Procedure for obtaining Minimal SOP.m4v
4.Design and Synthesis of Combinational circuits
1.Introduction to Logic Design.m4v
10.Comparator.mp4
11.Introduction to MUX.mp4
12.Proving MUX is functionally complete.mp4
13.Implementing functions with MUX example 1.mp4
14.Implementing functions with MUX example 2.mp4
15.multiplexer with enable input.mp4
16.relationship between select lines and inputs of a mux.mp4
17.cascading multiplexers - ex 1.mp4
18.cascading multiplexers - ex 2.mp4
19.cascading multiplexers - ex 3.mp4
2.AND-OR OR-AND realization.m4v
20.Expansion of multiplexers.mp4
21.Assigning select lines while expanding the MUX.mp4
22.Introduction to Demultiplexer.mp4
23.introduction to decoder.mp4
24.implementing functions with decoder example 1.mp4
25.implementing functions with decoder example 2.mp4
26.decoder for function implementation - ex3.mp4
27.converting one code to other code using decoder.mp4
28.ROM implementation using decoder.mp4
29.Implementing Functions using only Decoder.mp4
3.Minimum No of NAND gates example.m4v
30.Implementing Functions using Decoder and Multiplexer Example 1.mp4
31.Implementing Functions using Decoder and Multiplexer Example 2.mp4
32.Decoder with Enable Input.mp4
33.Constructing 3x8 Decoder using 1x2 Decode.mp4
34.Constructing 4x2 Decoder using 1x2 Decoder.mp4
35.Constructing 6x64 Decoder using 3x8 Decoder.mp4
36.Expansion of Decoder in general.mp4
37.Constructing 7x128 Decoder using 3x8 Decoder.mp4
38.Expansion of Decoders in another way.mp4
39.Address Expansion of ROM.mp4
4.NOR - NOR example.m4v
40.Word Expansion of ROM.mp4
41.Finding the Address ranges of Devices.mp4
42.Example on Enabling a Device.mp4
43.Finding the address ranges of Memory Devices.mp4
44.Introduction to Encoders.mp4
45.Priority Encoders.mp4
46.Introduction to Hazards.mp4
47.Hazards and test vectors.mp4
48.Examples on Test Vectors.mp4
49.Half Adder.mp4
5.Minimum No of NOR gates Example.mp4
50.Full Adder.mp4
51.Ripple Carry Adder.mp4
52.Carry Lookahead Adder.mp4
53.Carry look ahead adder implementation.mp4
54.Hybrid adder.mp4
55.Serial adder.mp4
56.Binary adder-subtractor.mp4
57.BCD adder.mp4
58.Invalid combinations for BCD adder.mp4
59.2 bit comparator.mp4
6.Minimum Noof NOR gates Example.mp4
60.3 4 bit comparators.mp4
61.Analysing all the cases of comparators.mp4
62.Gate 2016 question on multiplexer.m4v
63.Time complexity of ripple carry adder.m4v
64.Time complexity carry look ahead adder.m4v
7.EX-OR and EX-NOR implementation with NOR and NAND gates.mp4
8.Half adder.mp4
9.Half subtracter.mp4
5.Sequential Circuits
1.Introduction to sequential circuits.m4v
10.example on flipflop.mp4
11.example on flipflop 2.mp4
12.introduction to flipflop inter conversion.mp4
13.inter conversion of flipflops example.mp4
14.inter conversion of flipflops example 2.mp4
15.inter conversion of flipflops example 3.mp4
16.inter conversion of flipflops example 4.mp4
17.inter conversion of flipflops example 5.mp4
18.introduction to counters.mp4
19.asynchronous and synchronous counters.mp4
2.latch and flipflop.m4v
20.shift counters.mp4
21.mod 2 ring counters.mp4
22.mod 4 Johnson counter.mp4
23.mod 6 Johnson counter.mp4
24.MoD 3 ring counters.mp4
25.mod 4 gray counter using T FF.mp4
26.mod 4 gray counter using D FF.mp4
27.mod 4 gray counter using 1 D and 1 T flipflop.mp4
28.counter using two different FFs.mp4
29.Deriving the clock frequency.mp4
3.SR flipflop.m4v
30.self starting and free running.mp4
31.example on selfstarting and free running counters.mp4
32.counter using 3 different FFs.mp4
33.example on combinational circuits and FFs.mp4
34.introduction to asynchronous counters.mp4
35.Mod 8 up counter.mp4
36.Mod 4 up Counter.mp4
37.mod 4 down counter.mp4
38.Mod 8 random counter.mp4
39.model on analysis counting States and sequence generations.mp4
4.clocked flipflops.m4v
40.Applications of Flip flops.mp4
41.3 bit shift right register.mp4
42.Example 1 on shift right register.mp4
43.Example 2 on shift right register.mp4
44.Binary to gray convertor.mp4
45.Finding 2s complement.mp4
46.Gate 2001 on counting Sequence.mp4
47.Gate 2004 on SR-Latch.mp4
48.Gate 2014 on counter.mp4
49.Gate 2015 on sequence generation.mp4
5.positive level triggered.m4v
50.Gate 2015 on bit sequence.mp4
51.Gate 2015 on sequence genetaion.mp4
6.edge triggered.m4v
7.JK flipflop.mp4
8.T flipflop.mp4
9.D flipflop.mp4
6.Number system
1.Introduction to Number system.mp4
10.Example 7.mp4
11.Example 8.mp4
12.Complementary number system.mp4
13.Why we use complements.mp4
14.Subtraction in diminished radix complement.mp4
15.Examples on diminished radix complement.mp4
16.examples on subtraction in radix complement.mp4
17.Summary of subtraction using complements in case of unsigned numbers.mp4
18.signed number representation.mp4
19.example on signed number representations.mp4
2.Conversion to base 10.mp4
20.Ranges of signed number representations.mp4
21.Examples on Ranges.mp4
22.Sign bit extension.mp4
23.overflow.mp4
24.classification of binary codes.mp4
25.8421 Excess-3 3321 codes.mp4
26.Examples on codes.mp4
27.BCD addition.mp4
28.Excess-3 addition.mp4
29.Gray code.mp4
3.Conversion from base 10.mp4
30.Binary to gray and vice versa.mp4
31.Error detection.mp4
32.Error correction.mp4
33.Hamming code.mp4
34.Examples on Hamming code.mp4
35.Floating point Conversion.mp4
36.Floating point representation.mp4
37.Floating point representation.mp4
38.Floating point representation Example 1.mp4
39.40 Example 2.mp4
4.Minimum number of bits required for inter conversion - ex 1.mp4
40.Example 3.mp4
41.Introduction to Floating point representation.mp4
42.Introduction to IEEE Standards.mp4
43.Single Precision.mp4
44.Double precision.mp4
45.Example 1 on single precision.mp4
46.Example 2 on Single Precision.mp4
47.Example 1 on double Precision.mp4
48.Example 2 on Double Precision.mp4
49.Example on single and double Precision.mp4
5.Minimum number of bits required for inter conversion - ex 2.mp4
50.Gate 2016 on number of integers.mp4
51.Binary multiplication(partial sum method).mp4
52.Idea behind Booths algorithm.mp4
53.Booths algorithm example.mp4
54.Booths algorithm.mp4
55.Booth algorithm operations flow.mp4
56.Advanteges and Dis- Advantages of Booths algorithm.mp4
57.Example on fractional form.mp4
58.Example on fractional and implicit forms.mp4
6.Example 3.mp4
7.Example 4.mp4
8.Example 5.mp4
9.Example 6.mp4
7.Practice Questions
1.Practice Questions and Solutions Set-1.pdf
2.Practice Questions and Solutions Set-2.pdf
3.Practice Questions set-3.pdf
4.Practice Questions set-3 Solutions.pdf
5.Practice Questions and Solutions Set-4.pdf
7.Practice Questions and Solutions Set-5.pdf
8.Practice Questions and Solutions Set-6.pdf
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